#### Ron J. Bolton B.E., M.Sc., Ph.D.

Professor Emeritus of Electrical and Computer Engineering

- Room 3B03 Engineering Building
- (306) 966-5412
- ron.bolton@usask.ca
- http://www.engr.usask.ca/faculty.php?ron.bolton

Biography

Ronald J. Bolton is currently a Professor of Electrical Engineering at the University of Saskatchewan and Adjunct Scientist at Telecommunications Research Laboratories (TRLabs) in Saskatoon. Ron received B. Eng. and M.Sc. degrees from the University of Saskatchewan in 1972 and 1978 respectively and a Ph.D. degree from the University of Queensland in 1983. He presently teaches undergraduate and graduate courses in integrated circuit design, advanced electronics and pattern recognition. Current research interests are in VLSI design of application specific integrated circuits (ASICs).

While on sabbatical leaves from the University, he has worked with the Canadian Microelectronics Corporation (CMC) in 1995 and Wavecom Electronics Ltd. (now VCom Electronics Ltd.) in 2003.

Dr. Bolton is a Registered Proessional Engineer in Saskatchewan, a Member of the Institute of Electrical and Electronics Engineers (IEEE) and founder and president of Professional Special System Technologies Inc. (PSST).

For more information on TRLabs, you can visit its official homepage:

http://www.trlabs.ca/

Publications

#### Selected Journal Papers

[7] | D.H.Y. Teng, R. Bolton and D.E. Dodds, 2001, "A VHDL Library for Current-Mode CMOS Multiple-Valued Logic", Multiple Valued Logic - an International Journal, Vol. 7, pp. 49-73. [PDF] |

[6] | A.K. Jain, R.J. Bolton and M.H. Abd-El-Barr, 1993. "CMOS Multiple-Valued Logic Design - Part I: Circuit Implementation", IEEE Transactions on Circuits and Systems - I: Fundamental Theory and Applications. Vol. 40, No. 8, August pp. 503-514. |

[5] | A.K. Jain, R.J. Bolton and M.H. Abd-El-Barr, 1993. "CMOS Multiple-Valued Logic Design - Part II: Function Realization", IEEE Transactions on Circuits and Systems - I: Fundamental Theory and Applications. Vol. 40, No. 8, August, pp. 515-522. |

[4] | A.K. Jain, M.H. Abd-El-Barr,and R.J. Bolton, 1992. "A New Structure for CMOS Realization of MVL Functions", International Journal of Electronics, Vol. 74, No. 2, February, pp. 251-263. |

[3] | M.A. Bree, D.E. Dodds, R.J. Bolton, S. Kumar and B.L.F. Daku, 1992. "A Modular Bit-Serial Architecture for Large-Constraint-Length Viterbi Decoding", IEEE Journal of Solid-State Circuits, Volume 27, No. 2, February, pp. 184-190. [PDF] |

[2] | R.J. Bolton and L.C. Westphal, 1981. "Preliminary Results in Display and Abnormality Recognition of Hilbert Transformed ECG's", Medical and Biological Engineering and Computing, Vol. 19 (3), May, pp. 377-388. |

[1] | R.J. Bolton, R.C. Craig and L.C. Westphal, 1981. "Computer-Aided Design of Recursive Digital Filters with Coefficients Having Restricted Minimal Representation", IEEE Transactions on Acoustics, Speech and Signal Processing, Vol. ASSP-29 (6), December, pp. 1205-1208. |

#### Conference Publications

[20] | Daniel H. Y. Teng and Ronald J. Bolton, 2005, "PERFORMANCE EVALUATION OF MULTIPLE-VALUED LOGIC CIRCUITS USING STATISTICAL APPROACH", Proceedings of IEEE Canadian Conference on Electrical and Computer Engineering, May 1-4, Saskatoon, Canada, pp. 0300-0303. [PDF] |

[19] | Darrell Laturnas and Ron Bolton, 2005, "Dynamic Silicon Firewall", Proceedings of IEEE Canadian Conference on Electrical and Computer Engineering, May 1-4, Saskatoon, Canada, pp. 0304-0307. [PDF] |

[18] | Adam Ottley and Ron Bolton, 2005, "HARDWARE-ASSISTED LOSSLESS ECG CODER", Proceedings of IEEE Canadian Conference on Electrical and Computer Engineering, May 1-4, Saskatoon, Canada, pp. 0362-0365. [PDF] |

[17] | Bernard Boos, David Dodds, and R. Bolton, 2004 "High Speed Digital Signal Compensation on Printed Circuit Boards", CCECE 2004, Niagara Falls, May 2-5. [PDF] |

[16] | D. Teng and R. Bolton, 2004, "A Self-Restored Current-mode CMOS Multiple Valved Logic Design Technician and ITS Applications", ISMUL 2004, Toronto, May 19-22, pp 204-209. |

[15] | A.V. Dinh, R.J. Bolton, 2002. "High Speed Forward Error Correction IP Blocks for System-On-Chip", IEEE Canadian Conference on Electrical and Computer Engineering (CCECE'02) Proceedings, Winnipeg, Manitoba, May 12-15, Vol. 1, pp. 515-520. |

[14] | A.V. Dinh and R.J. Bolton, 2000. "A Low Latency Architecture for Computing Multiplicative Inverses and Divisions in GF(2m)", Canadian Conference on Electrical and Computer Engineering (CCECE 2000), Halifax, Nova Scotia, May 7-10, pp 43-47. |

[13] | A.V. Dinh, R.J. Palmer, R.J. Bolton, and R. Mason, 2000. "Multichannel Multipoint Distribution Service System Synchronization using a Global Positioning System Clock", Canadian Conference on Electrical and Computer Engineering (CCECE 2000), Halifax, Nova Scotia, May 7-10, pp 875-879. |

[12] | A. Dinh, R.J. Bolton, R.J. Palmer, and R. Mason, 1999. "Multi-channel Multi-point Distribution Service System Transceiver Implementation", Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM'99), August 22-24, Victoria, B.C., pp 242-245. |

[11] | H.Y. Teng, R.J. Bolton, A.K.Jain, R.D. Schmitz, and D.E. Dodds, 1999. "A VHDL Library for Current-Mode CMOS Multiple Valued Logic", Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM'99), August 22-24, Victoria, B.C., pp 432-435. |

[10] | H.Y. Teng and R.J. Bolton, 1999. "A Self-Restored Current Mode CMOS Multiple-Valued Logic Design Architecture", Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM'99), August 22-24, Victoria, B.C., pp 436-439. |

[9] | D.E. Dodds, R. Schmitz, R.J. Bolton, R. Mason, and A. Dinh, 1999. "Segmented Match Filter for Code-Phase Acquisition", Wireless'99, July 12-14, Calgary, Alberta, pp 159-169. |

[8] | A. Dinh and R.J. Bolton, 1999. "Design of a High-Speed (255, 239) Reed-Solomon Codec for MMDS Transceiver", WESCANEX'99, Calgary, Alberta, 5 pages. |

[7] | D.E. Dodds, R. Mason, R. Schmitz, A. Dinh and R. Bolton, 1998. "A Segmented Match Filter for CDMA Codephase Acquisition", Canadian Conference on Electrical and Computer Engineering, Waterloo, ON, May 24-28, VI, p. 253-256. |

[6] | A.K. Jain, M.H. Abd-El-Barr and R.J. Bolton, 1995. "Current-Mode CMOS Multiple-Valued Logic Function Realization Using a Direct Cover Algorithm", Proceedings of the 25th International Symposium on Multiple-Valued Logic, Bloomington, Indiana, May 22-26, 6 pages. |

[5] | A.K. Jain, R.J. Bolton, M.H. Abd-El-Barr and C. Cheung, 1993. "On Multiple-Valued Logic Design of Neural Networks", Proceedings of the IEEE 36th Midwest Symposium on Circuits and Systems, Detroit, Michigan, August 16-18, 4 pages. |

[4] | M.H. Abd-El-Barr, R.J. Bolton and A.K. Jain, 1993. "Current-Mode CMOS Realization of a Multiple-Valued Logic Neurode", IEEE Wescanex '93 Conference Proceedings, Saskatoon, Saskatchewan, May 17-18, pp. 201-207. |

[3] | A.K. Jain, R.J. Bolton, M.H. Abd-El-Barr and V. Fortugno, 1992. "Current-Mode CMOS Realization of MVL Operators", Canadian Conference on VLSI Technical Digest, Halifax, Nova Scotia, October 18-20, pp. 276-283. |

[2] | A.K. Jain, R.J. Bolton and M.H. Abd-El-Barr, 1991. "A New TSUM-Based Minimization Technique for Multi-Valued Logic Function Implementation Using Current-Mode CMOS", IEEE International Symposium on Integrated Circuits '91, September 11-13, Singapore, pp. 622-627. |

[1] | M.H. Abd-El-Barr, H. Choy, A.K. Jain and R.J. Bolton, 1991. "A Comparative Study of Programmable Realization Techniques of Multi- Valued Multi-Threshold Functions", IEEE International Symposium on Multi-Valved Logic, Victoria, British Columbia, May 26-29, pp. 72-381. |

Graduate Students

#### Graduate Students

##### Darrell K. Laturnas

MSc, Dynamic Silicon Firewall##### Adam Ottley

MSC, ECG Compression for use in Holter Monitoring##### Xiangling Wang

MS., Numerical Implementation of the Hilbert Transform#### Former Graduate Students

##### Reza Ahrabian

MEng##### Bernard Boos

MSc, "High Speed Digital Signal Compensation on Printed Circuit Boards", February 2004. (with D.E. Dodds)##### Jin Cheng

MSc, "Silicon Firewall Prototype", December 2003.##### H.Y. Teng

Ph.D., "Self-Restored Current-Mode CMOS Multiple-Valued Logic Design and Synthesis", December 2002.##### Benjamin Persson

M.Sc. "A Mixed Signal ASIC for CDMA Synchronization", August 2001.##### Tammy Yee

M.Sc. "Attitude Determination Using Stellar Images", March 1999.##### Totok Mujiono

M.Sc. "Investigation of a 900 MHz CMOS Fractional-N Phase-Locked Loop Based Frequency Synthesizer", March 1999.##### Renee Schmitz

M.Sc. "A Segmented Matched Filter for Spread Spectrum Codephase Acquisition", November 1998. (Co-supervised with D. Dodds)##### Hsiang-Yung Teng

M.Sc. "High-Level Simulation of Multiple-Valued Logic Systems", August 1996.##### Vincenzo M. Fortugno

M.Sc. "Design and Test of a Multiple-Valued Logic CMOS Standard Cell Library", December 1995. (Co-supervised with Abd-El-Barr)##### Charlie Cheung

M.Sc. "Implementation of Standard Cell Library for Current-Mode Multiple-Valued Logic Circuit Using CMOS Technology", April 1995.##### A.K. Jain

Ph.D., "Multiple-Valued Logic Design in Current-Mode CMOS"; November 1993. (Co-supervised with M.H. Abd-El-Barr).##### R. Cram

M.Sc., "The Design of an ECG Morphology Processor Chip"; November 1990.##### A.S.M. Lau

M.Sc., "An Investigation of Integrated Circuit Hardware Design Rule Checking Using the TMS 34010"; August 1990.##### G. Lakshmikanth

M.Sc., "Design and Implementation of a VLSI Systolic Array for the Transportation Simplex Algorithm"; July 1989. (Co-supervised with M. Abd-El-Barr)##### Y. Yuan

M.Sc. "Analysis of ECG Body Surface Potentials"; November 1988. (Co-supervisor with V. Pollak, K. Takaya).##### E.P. Komarla

M.Sc. "An Algorithm for Garbage Collection in Multicomputer Systems"; September 1988. (Co-supervisor with C.J. McCrosky).##### K. Goulet

M.Sc. "An Integrated Circuit for ECG Processing"; August 1987.##### C.S.R. Moturu

M.Sc. "A Layout Automator For VLSI Circuit Design Using Standard Cells"; January 1987.##### A.K. Jain

M.Sc. "Implementation Approaches in the Computer-Aided Design of CSD Digital Filters"; October 1986.Teaching

##### EP155

Electric and Magnetic Circuits ITopics include Coulomb's law, sources of dc potential, resistance, conductance, Ohm's law, power and energy, ammeters, voltmeters, voltage dividers, ohmmeter, Kirchhoff's laws, series and parallel circuits, circuit analysis techniques, Wheatstone bridge, electrostatic fields, dielectric materials, capacitance, series and parallel arrangement of capacitors, transients in R-C circuits.

http://www.usask.ca/calendar/ep/155

##### EE432

VLSI Circuit DesignA general introduction to VLSI design, simulation and testing. This includes CMOS cell design, logic simulation, circuit simulation and system design.

http://www.usask.ca/calendar/ee/432

##### EE802

Advanced VLSI DesignA study of semiconductor devices with special emphasis placed on device operation in VLSI circuits. Topics include device physics, electrical characteristics, computer simulation of circuits, speed-power-area considerations, circuit synthesis and CMOS integrated circuit design. Additional lecture topics as requested may be given. A design project is also required.

http://www.usask.ca/calendar/ee/802

##### EE813

Introduction to Pattern RecognitionA basic introduction to pattern recognition systems, Topics include vector space representation of patterns, supervised and unsupervised systems, distance matrices, discriminant functions, probability density and parameter estimation, maximum likelihood and minimum risk classification, potential functions, feature selection and clustering. A design project is also required.

http://www.engr.usask.ca/classes/EE/813/

Research Projects

Dr. Bolton's research experience has been in the areas of multiple-valued logic circuits, computer-aided design systems, and pattern recognition. In particular he has carried out work on Application Specific Integrated Circuits (ASICs) in the areas of ECG processing, Viterbi decoding, and Canonical-Signed Digit code filters. He has developed software for use with standard cell libraries for integrated circuit design software. He is particularly interested in the area of minimization and synthesis of multiple-valued logic functions.

His research on multiple-valued logic has lead to the specification of a new, functionally-compete set of operators for use in multiple-valued logic. Using this set of operators it is possible to more efficiently (based on the number of product terms) realize circuit functionality. This research was done in cooperation with A.K. Jain and M.H. Abd-El-Barr.

His development of a Canadian Microelectronics Corporation (CMC) Analog Artist version of the Gennum linear bipolar array GA911 technology allows the CMC to offer an undergraduate design technology to Canadian university members at no cost. This initiative is supported by facilities available to the CMC through Gennum and Tundra Semiconductor.

His research in pattern recognition has lead to an ECG analysis systems capable of identifying harmful ECG morphologies and arrhythmia. This system is based upon Hilbert Transform processing of the ECG data and subsequent recognition using custom ICs and/or software based systems. The process is particularly suitable to real-time processing of Holter type ECGs since it can lead to long term monitoring.

Current research projects include work in the use of current-mode CMOS logic multiple-valued logic in the area of neural networks. This includes the use of VHDL (using a mixed-signal current-mode CMOS logic multiple-valued library developed with H-Y. Teng and A.K. Jain) to specify the structure of the networks and to use synthesis to construct them. Another research project is the multi-disciplinary NITEOWL (Nightsky Imaging and Tomography Experiment on Ozone using Light from Stars) project. This project combines expertise from the departments of Engineering Physics, Electrical Engineering, Mechanical Engineering, Mathematics and Statistics, and Commerce. The project has reached the final proposal stage with the results of the Canadian Space Agency Small Payloads Program Application Opportunity known in early 1997. Related to this project will be the development of an Attitude Video Camera pattern recognition software system and the development of a mission simulator.