Seok-Bum Ko

     Seok-Bum Ko  Ph.D., P.Eng.

    Professor of Electrical and Computer Engineering
    Graduate Chair, Electrical and Computer Engineering

    Biography

    Ph.D., Dept. of Electrical and Computer Engineering, Univ. of Rhode Island, USA

    Technical Staff, Korea Telecom Research and Development Center, Rep. of Korea

    M.Sc., Dept. of Computer Engineering, Chonbuk National University, Rep. of Korea

    B.Sc., Department of Computer Engineering, Chonbuk National University, Rep. of Korea

    Publications

    Selected Journal Papers since 2013

    1. J. Yepez and S. Ko* , “Improved License Plate Localization Algorithm Based on Morphological Operations,” accepted to IET Intelligent Transport Systems. February 8, 2018

    2. S. Venkatachalam and S. Ko* , “Approximate Sum of Products Designs based on Distributed Arithmetic,” accepted to IEEE Transactions on Very Large Scale Integration Systems. March 4, 2018

    3. H. Zhang, D. Chen, and S. Ko* , 2017. “High Performance and Energy Efficient Single-Precision and DoublePrecision Merged Floating-Point Adder on FPGA,” IET Computers & Digital Techniques, Vol. 12, Iss. 1, pp. 20-29.

    4. H. Zhang, D. Chen, and S. Ko* , 2017. “Area and Power Efficient Iterative Single-Precision and DoublePrecision Merged Floating-Point Multiplier on FPGA,” IET Computers & Digital Techniques. , Vol. 11, Iss. 4, pp. 149-158.

     5. Z. Jiang, J. Yepez, S. An and S. Ko* , 2017. “Fast, accurate and robust retinal vessel segmentation system,” Elsevier Biocybernetics and Biomedical Engineering, Vol. 37, Iss. 3, pp. 412-421.

    6. S. Venkatachalam and S. Ko* , 2017. “Design of Power and Area Efficient Approximate Multipliers” IEEE Transactions on Very Large Scale Integration Systems, Vol. 25, Iss. 5, pp. 1782-1786.

    7. C. Loi and S. Ko*, 2016. “Parallelization of Scalable Elliptic Curve Cryptosystem Processors in GF(2^m),” Elsevier Microprocessors and Microsystems, Vol. 45, Part A, pp. 10–22.

    8. S. Kathirvel, R. Jangre and S. Ko*, 2016. “Design of a Novel Energy Efficient Topology for Maximum Magnitude Generator,” IET Computers & Digital Techniques, Vol. 10, Iss. 3, pp. 93-101.

    9. L. Han, H. Zhang and S. Ko*, 2016. “Decimal Floating-Point Fused Multiply-Add with Redundant Internal Encodings,” IET Computers & Digital Techniques, Vol. 10, Iss. 4, pp. 147-156.

    10. A. Kaivani and S. Ko*, 2016. “Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 24, No. 3, pp. 1208-1211.

    11. C. Loi and S. Ko*, 2015. “Scalable Elliptic Curve Cryptosystem FPGA Processor for NIST Prime Curves,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 23, No. 11, pp. 2753-2756.

    12. L. Han, H. Zhang and S. Ko*, 2015. “Area and Power Efficient Decimal Carry Free Adder,” IET Electronic Letters, Vol. 51, Iss. 23, pp. 1852-1854.

    13. M. Kumar, M. S. Gaur, V. Laxmi, M. Daneshtalab, S. Ko and M. Zwolinski, 2015. “A Novel Highly Adaptive Routing for Networks-on-Chip,” IET Electronics Letters, Vol. 51, No. 25, pp. 2092-2094. 14. A. Kaivani and S. Ko*, 2015. “Area Efficient Floating-Point FFT Butterfly Architectures Based on MultiOperand Adders,” IET Electronics Letters, Vol. 51, No. 12, pp. 895-897.

    15. C. Lal, V. Laxmi, M. Gaur, and S. Ko*, 2015. “Bandwidth-aware routing and admission control for efficient video streaming over MANETs,” Springer Wireless Networks, Vol. 21, Iss. 1, pp. 95-114. 16. A. Kaivani and S. Ko*, 2014. “'Improved Design of High-Frequency Sequential Decimal Multipliers,” IET Electronics Letters, Vol. 50, Iss. 7, pp. 558-560.

    16. X. Jin, B. Daku, and S. Ko*, 2014. “Improved GPU SIMD Control Flow Efficiency via Hybrid Warp Size Mechanism,” Elsevier Journal of Microprocessors and Microsystems, Vol. 38, Iss. 7, pp. 717-729.

    17. K. Swaminathan, G. Lakshminarayanan, and S. Ko*, 2014. “Design and Verification of an Efficient WISHBONE-based Network Interface for Network on Chip,” Elsevier Computers and Electrical Engineering, Vol. 40, Iss. 6, pp. 1838-1857.

    18. L. Han, A. Kaivani, and S. Ko* , 2013. “Area Efficient Sequential Decimal Fixed-point Multiplier,” Journal of Signal Processing Systems, Springer, Vol. 75, Iss. 1, pp. 39-46.

    19. A. Kaivani and S. Ko* , 2013. “Decimal Division Algorithms: The Issue of Partial Remainders,” Journal of Signal Processing Systems, Springer, Vol. 73, Iss. 2, pp. 181-188.

    20. C. Loi and S. Ko* , 2013. “High Performance Scalable Elliptic Curve Cryptosystem Processor for Koblitz Curves,” Journal of Microprocessors and Microsystems, Elsevier, Vol. 37, Iss. 4-5, pp. 394-406.

    21. A. Kaivani and S. Ko* , 2013. “Decimal SRT Square Root: Algorithm and Architecture,” Circuits, Systems & Signal Processing (CSSP), Springer, Vol. 32, Iss. 5, pp. 2137-2150.

    22. K. Swaminathan, G. Lakshminarayanan, and S. Ko* , 2013. “High Speed Generic Network Interface for Network on Chip using Ping Pong Buffers,” Journal of Low Power Electronics, American Scientific Publishers, Vol. 9, No. 3, pp. 322-331.

    23. C. Vennila, A. Patel, G. Lakshminarayanan and S. Ko* , 2013. “Dynamic Partial Reconfigurable Viterbi Decoder for Wireless Standards,” International Journal on Computers and Electrical Engineering, Elsevier, Vol. 39, Iss. 2, pp. 164-174.

    24. L. Han and S. Ko* , 2013. “High Speed Parallel Decimal Multiplication with Redundant Internal Encodings,” IEEE Transactions on Computers, Vol. 62, No. 5, pp. 956-968.

    25. Y. Choi, Q. Zhang, and S. Ko* , 2013. “Noninvasive cuffless blood pressure estimation using pulse transit time and Hilbert-Huang transform,” International Journal on Computers and Electrical Engineering, Elsevier, Vol. 39, Iss. 1, pp. 103-111.

    Accepted/Published Referred Conference Publications since 2013

    [1] J. Yepez, X Shi and S. Ko, "An FPGA-Based Closed-Loop Approach of Angular Displacement for a Resolver-to-Digital-Converter." accepted to International Symposium on Circuits and Systems, May, 2018
    [2] H. Zhang, H. Lee, and S. Ko, "Efficient Fixed/Floating-Point Merged Mixed-Precision Multiply-Accumulate Unit for Deep Learning Processors," accepted to International Symposium on Circuits and Systems, May 2018
    [3] S. Venkatachalam, H. Lee, and S. Ko, "Power Efficient Approximate Booth Multiplier," accepted to International Symposium on Circuits and Systems, May, 2018
    [4] X. Shi, J. Dai, X. Luo, J. Yepez, and S. Ko, "Foreground-Background Separation Guided by Statistical Features of Surveillance Video," International Conference on Consumer Electronics, October 2016
    [5] C. Loi and S. Ko, 2016. "Scalable ECC FPGA Processor for NIST Prime Curves," IEEE International Symposium on Circuits and Systems, May.
    [6] A. Kaivani and S. Ko, 2016. "FP Butterfly Architecture based on Binary Signed-Digit Representation,"  IEEE International Symposium on Circuits and Systems, May.
    [7] M. Kumar, V. Laxmi, M. Gaur, M. Daneshtalab, P. Srivastava, S. Ko, M. Zwolinkski, 2014. "A novel non-minimal/minimal turn model for highly adaptive routing in 2D NoCs," IEEE/ACM International Symposium on Networks-on-Chip, Sep., pp.184-185.
    [8] S. Nambiar, K. Swaminathan, G. Lakshminarayan, S. Ko, 2014. "Central Switch Noded Mesh Architecture (CSNM), IEEE International Conference on Electronics and Communication Systems, Feb., pp.1-5.
    [9] S. Nambiar, S. Kathirvel, G. Narayanan, and S. Ko, 2014, "QaMC - QoS Aware Multicast router for NoC Fabric," CCECE, Toronto, May, CD.
    [10] S. Kathirvel, R. Jangre, S. Nambiar, G. Narayanan, and S. Ko, 2014, "A Novel Hybrid Topology for NoC," CCECE, Toronto, May, CD.
    [11] C Loi and S.Ko, 2014, "FPGA Implementation of Low Latency Scalable Elliptic Curve Cryptosystem Processor in GF(2^m)," IEEE International Symposium on Circuits and Systems, Melbourne, Australia, June pp. 822-825.
    [12] A. Kaivani and S. Ko, 2014, "High-Speed FFT Processors Based on Redundant Number Systems," IEEE International Symposium on Circuits and Systems, Melbourne, Australia, June, pp. 2237-2240.
    [13] M. Kumar, Pankaj, V. Laxmi, M Gaur, and S. Ko, 2013, "Reconfigurable distributed fault tolerant routing algorithm for on-chip networks," IEEE Symposium Defect and Fault Tolerance in VLSI and Nanotechnology Systems, New York, USA, Oct. pp. 290-295.
    [14] M. Kumar, V. Laxmi, M. Gaur, S. Ko, and M. Zwolinski, 2014, "CARM: Congestion Adaptive Routing Method for On Chip Networks," IEEE International Conference on VLSI Design, India, Jan. pp. 240-245.
    [15] M. Kumar, V. Laxmi, M. Gaur, M. Daneshtalab, S. Ko and M Zwolinski, 2014, "A Low-Cost Highly Adaptive and Congestion-aware Routing for 3D On Chip Networks," accepted to 24th ACM Great Lake Symposium on VLSI (GLSVLSI), Houston, USA, May.
    [16] M. Kumar, D. Thakyal, S. Nambiar, G. Lakshminarayanan, and S. Ko, 2014, "Enhanced Noxim Simulator for performance evaluation of NoC Topologies" accepted to Recent Advances in Engineering and Computational Sciences, India, May.
    [17] K. Swaminathan, G. Lakshminaryanan, F. Lang, M. Fahmi, and S. Ko, 2013. "Design of a Low Power Network Interface for Network on Chip," IEEE Canadian Conference on Electrical and Computer Engineering, Regina, SK, May, CD.
    [18] C. Vennila, Suresh. K, R. Rathor, G. Lakshminarayanan, and S. Ko, 2013. "Dynamic Partial Reconfigurable Adaptive Transciever for OFDM based Cognitive Radio," IEEE Canadian Conference on Electrical and Computer Engineering, Regina, SK, May, CD.
    [19] A. Kaivani, and S. Ko, 2013. "Decimal Signed Digit Addition Using Stored Transfer Encoding," IEEE Canadian Conference on Electrical and Computer Engineering, Regina, SK, May, CD.

    Patents

    [4] Seok-Bum Ko, J. Park and H. Chong, "AAL1 Receiving Apparatus for CBR (Constant Bit Rate)," Reg. No. 0271521, Korea, August 17, 2000
    [3] Seok-Bum Ko, J. Park and H. Chong, "AAL1 Transmitting Apparatus for CBR," Reg. No. 0271522, Korea, August 17, 2000
    [2] J. Park and J. Kwon and Seok-Bum Ko, "Fitting Device in ATM System," Reg. No. 0257556, Korea, March 2. 2000
    [1] J. Park and J. Kwon and Seok-Bum Ko, "Multiplexer and Demultimlexer of ATM Transfer Mode Cell in Multimedia Service Processing," Reg. No. 0257557, Korea, March 2, 2000

    Research Grants

    Graduate Students

    Current Graduate Students

    Suganthi Venkatachalam, Ph.D., approximate computing
    Hao Zhang, Ph.D., computer arithmetic
    Juan Yepez, Ph.D., deep learning application
    Yi Wang, M.Sc., deep learning application

    Former Graduate Students

    MSc
    Ali Malik
    Yongsoon Lee
    Kelsey Muma
    Amitoz Ralhan
    Yu Zhang
    Qiao Zhang
    Cinnati Loi
    Atahar Mostafa
    Xingxing Jin
    Zhuo Wang
    Shariq Sami
    Sen An
    Hao Zhang
    Juan Yepez

    PhD
    Dongdong Chen
    Han Liu
    Amir Kaivani
    Cinnati Loi

    Teaching

    EE 232
    Digital Electronics

    An introduction to digital logic including combinational and sequential logic devices and circuits. Covers the range from the fundamentals of Boolean algebra and the binary number systems to combinational and sequential circuit functional blocks such as adders, multiplexers, counters and state machines. Some coverage is also given to electronic characteristics of real logic devices and field programmable gate arrays (FPGA).

    http://www.engr.usask.ca/classes/EE/232/
    EE 331
    Microprocessor Hardware and Software

    Covers the architecture and operation of microprocessors and memory devices, linking together of logic devices. The assembler language is introduced to program low level functionality of microprocessors.

    http://www.engr.usask.ca/classes/EE/331/
    EE 395
    Electrical Engineering Design

    Covers the "top down" approach applied to engineering design. The students will exercise the approach by designing, building and testing one or two projects. The course also includes aspects of manufacturing engineering and, project organization and control.

    http://www.engr.usask.ca/classes/EE/395/
    CME 433
    Digital Systems Architecture

    http://www.engr.usask.ca/classes/CME/433/
    CME 451
    Transportation Networks

    http://www.engr.usask.ca/classes/CMEE/451/
    EE 800
    Circuit Elements in Digital Computations

    http://www.engr.usask.ca/classes/EE/800/

    Research Projects

    Research Projects

    Efficient Implementation of Decimal/Binary Floating Point Unit in FPGAs

    Efficient FPGA Realizations Based on AND/XOR Expressions

    Efficient Implementation of Advanced Encryption Standard in FPGAs

    Deep Learning processor architecture

    Collaborative Research

    Biological Sensor technology, NSERC CRD

    NoC research, PMC-Sierra

    Low-power floating point arithmetic unit, IBM

    Near-falls and falls Detection System, Natural Science and Engineering Research Council of Canada Strategic Project Grants

    Bluetooth Enabled Radiation Detectors, MITACS Accelerate with Environmental Instruments Canada